Variable duty-cycle and frequency oscillator circuit

ABSTRACT

An oscillator circuit having a variable duty-cycle and frequency, both of which are determined by the amplitude of an input analog signal. The output of the invented circuit is a waveform having a fixed off-time and a variable on-time, the latter being inversely proportional to the amplitude of the input signal voltage level. The significant characteristic of the output waveform is that in each cycle the product of (i) the output voltage and (ii) the on-time is substantially constant. This output characteristic of the present invention makes it useful in a number of applications, one of which is as a voltage regulator. The invented circuit comprises, in part, (i) a pair of switches, typically transistors, which cyclically and alternately switch on and off, and (ii) a pair of charging capacitors which cyclically and alternately control the switching times of the switches. The fixed time constant with which one of the two charging capacitors is charged determines the fixed off-time of the circuit&#39;&#39;s output waveform, while the variable charging rate of the second capacitor, a rate which is proportional to the input signal voltage, determines the variable on-time of the output waveform.

Elite States Patent 1 Chopra June 19, 1973 VARIABLE DUTY-CYCLE AND FREQUENCY OSCILLATOR CIRCUIT [75] Inventor: Jagdish C. Chopra, Inglewood, Calif.

[73] Assignee: TRW Inc., Los Angeles, Calif.

[22] Filed: Sept. 20, 1971 [21] Appl. No.: 182,062

[52] US. Cl. 331/113 R, 332/14 [51] Int. Cl. H03k 3/282 [58] Field of Search 331/113; 332/14 [56] References Cited UNITED STATES PATENTS 3,253,186 5/1966 Rogers et al 331/113 FOREIGN PATENTS OR APPLICATIONS 1,429,616 1/1966 France 331/113 Primary Examiner-John Kominski AttameySpensley, Horn & Lubitz [57] ABSTRACT An oscillator circuit having a variable duty-cycle and frequency, both of which are determined by the amplitude of an input analog signal. The output of the invented circuit is a waveform having a fixed off-time and a variable on-time, the latter being inversely proportional to the amplitude of the input signal voltage level. The significant characteristic of the output waveform is that in each cycle the product of (i) the output voltage and (ii) the on-time is substantially constant. This output characteristic of the present invention makes it useful in a number of applications, one of which is as a voltage regulator. The invented circuit comprises, in part, (i) a pair of switches, typically transistors, which cyclically and alternately switch on and off, and (ii) a pair of charging capacitors which cyclically and alternately control the switching times of the switches. The fixed time constant with which one of the two charging capacitors is charged determines the fixed off-time of the circuits output waveform, while the variable charging rate of the second capacitor, 21 rate which is proportional to the input signal voltage, determines the variable on-time of the output waveform.

1 Claim, 3 Drawing Figures v trams VARIABLE DUTY-CYCLE AND FREQUENCY OSCILLATOR CIRCUIT BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to the field of electronic frequency oscillator circuits, and, more particularly, to a variable duty-cycle and frequency oscillator whose duty-cycle and frequency are each a function of the amplitude of an input analog signal.

2. Prior Art Electronic oscillator circuits whose duty-cycles and frequencies vary as a function of the circuits input voltage level, have been disclosed in the prior art. Although these circuits are functionally similar to the invented circuit, there are significant differences between them and that of the present invention. Firstly, the circuits disclosed in the prior art have typically required the utilization of magnetic components, such as transformers or saturable reactors, in order to provide the desired function. Since such magnetic components are relatively large and bulky, these circuits have not been amenable to microminiaturization. Secondly, the circuits disclosed by the prior art have also typically required a relatively large number of components. This factor has increased their cost and further reduced their usability in microelectronic applications. In recent years the number of microelectronic applications which require oscillators having the characteristics of the invented circuit have increased, particularly in the area of computer power supplies and laser power supplies. Thus, it has become apparent that the circuits disclosed in the prior art are inherently incapable of fulfilling the requirements for microelectronic circuitry in these applications. The present invention, on the other hand, discloses an oscillator circuit which can provide the desired function without the use of any of the magnetic components relied upon in the past. The invented circuit, therefore, is amenable to fabrication by microelectronic techniquesand, as a result, it can satisfy the microminiaturization requirements imposed in many applications. A further advantage of the present invention over the prior art is that it produces the desired function with a minimum of components, thereby achieving an economic benefit as well as further miniaturization.

BRIEF SUMMARY OF THE INVENTION The present invention is comprised, in part, of (i) two switches, preferably transistors, which cyclically and alternately switch from a fully conducting state to a fully non-conducting state, and (ii) a pair of charging capacitors. With reference to embodiments of the present invention using transistors as switches, the plates of the first charging capacitor are connected to the collector of the first switching transistor and to the base of the second switching transistor respectively, while the plates of the second charging capacitor are connected to the collector of the second switching transistor and to the base of the first switching transistor respectively. (Hereinafter the plates of the charging capacitors which are connected to the collectors of their respective switching transistors will be referred to as the collector sides," while the sides of the charging capacitors which are connected to the bases of their respective switching transistors will be referred to as the base sides). The emitters of each of the switching transistors are connected to the circuits ground.

During a first phase of each cycle, the first charging caacitor is charged through a first path defined by a charging resistor and the first switching transistor, the latter being in its fully conducting state. The charging rate is determined by the fixed RC time constant of the path; i.e., by the product of the resistance and capacitance of the path. During a second phase of each cycle, the second charging capacitor is charged through a second path defined by at least one transistor acting as a current source, and the second switching transistor, the latter being in its fully conducting state. As explained more fully hereinbelow, the charging rate of the second charging capacitor is directly proportional to the amplitude of the input signal.

The operation of the invention circuit is basically as follows: During the first phase of each cycle, the first switching transistor is in its fully conducting state, thereby providing an electrical path through which the first charging capacitor is charged (with a fixed time constant, as indicated above). During this phase, the base side of the first charging capacitor charges toward +V volts, where V, volts is a substantially constant power supply voltage. The voltage on the base side of the first charging capacitor determines whether the second switching transistor is in its conducting or nonconducting state. Thus, until the voltage on the base side of the first charging capacitor reaches the base-toemitter voltage of the second switching transistor, V the latter is negatively biased to be in a non conducting state.

At the instant the voltage on the. base side of the first charging capacitor reaches V the second switching transistor is turned on, causing the voltage on the base side of the second charging capacitor to drop instantly to -V volts. This negative voltage acts to bias off the first switching transistor. Thus, at this instant the first phase of the cycle ends and the second phase commences.

During the second phase of each cycle, the base side of the second charging capacitor charges toward +V, volts. The voltage on the base side of the second charging capacitor detemines whether the first switching transistor is in its conducting or non-conducting state. Thus, until the voltage on the base side of the second charging capacitor jreaches a voltage equal to the baseto-emitter voltage of the first switching transistor, V the first switching transistor is negatively biased to be in a non-conducting state. This is a mirror image of what takes place during the first phase of the cycle, except for the following significant difference, to wit: the second charging capacitor is charged by a current which is directly proportional to the input signal voltage. Thus, unlike the first charging capacitor, the second charging capacitor is not charged at an exponential rate determined by a fixed time constant, but, instead, by a variable current. As the input signal voltage increases, the charging current increases; consequently, less time is required for the base side of the second charging capacitor to reach vg1g ,VOitS. Conversely, as the input signal voltage decreases, the charging current decreases, requiring more time for the second charging capacitor to reach VB volts.

At the instant the voltage on the base side of the second charging capacitor reaches V the first switching transistor is turned on, causing the voltage on the base output transistor and the circuits input signal is con- V nected to the collector. The emitter of the output transistor'is connected to the output terminal of the invented circuit. The gating signal determines the conducting or non-conducting state of the output transistor. Thus, the output of the invented circuit is the product of the input signal and the operating function of the output transistor. During the first phase of each cycle, the output transistor is in a non-conducting state, and

no voltage appears at the output of the circuit. Duringthe second phase of the cycle, the gating signal causes the output transistor to conduct for a variable time interval which is inversely proportional to the input signal amplitude. Thus, for the duration of the second phase, the output signal is approximately equal to the input signal. Consequently, the product of the output voltage and the duration of the second phase remains substantially constant during each cycle.

The invented circuit, therefore, responds to a variable analog input signal by producing an output signal whose waveform has the following characteristics: (i) a constant off-time during which the output voltage is approximately zero volts; (ii) a variable on-time during which the output voltage is approximately equal in amplitude to that of the input signal; and (iii) a substantially constant average output voltage level, independent of variations in the amplitude of the input signal.

Thus, it is a principal object of the present invention to provide a variable duty-cycle and frequency oscillator circuit without utilizing any magnetic components.

It is another principal object of the present invention to provide a variable duty-cycle and frequency oscillator circuit whose average output voltage remains substantially constant despite variations in the amplitude of its inputsignal.

A still further object of this invention is to implement a variable duty-cycle and frequency oscillator circuit with a minimum of components.

The novel features which are characteristic of the present invention will be better understood from the following detailed description, reference being had to the accompanying drawings in which a presently preferred embodiment of this invention is illustrated by example.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation of a preferred embodiment of the present invention. In this drawing, capacitive components are designated by the symbol C, inductive components by L, resistive components by R, and transistors by Q. The subscript uniquely identifies the particular component.

FIG. 2 is a representation of the output voltage waveform of the circuit of FIG. 1.

FIG. 3 is a schematic representation of an application wherein the present invention is utilized as a voltage regulator.

DETAILED DESCRIPTION OF THE INVENTION With reference to FIG. 1, a preferred embodiment 10 of the present invention will now be described in detail. (Throughout the following description, all references to connections shall be understood to mean electric] connections.) Transistor Q, and 0 operating as electronic switches, have emitter legs 12 and 14, base legs 16 and 18, and collector legs 20 and 22, respectively. The emitter legs 12 and 14 of transistors Q, and Q respectively, are connected to a circuit ground point 15. The base leg 16 of transistor Q, is connected to a first side 16' of charging capacitor C,, and the base leg 18 of transistor O is connected to a first side 18 of charging capacitor C Similarly, collector leg 20 of transistor Q, is connected to a second side 20 of capacitor C and collector leg 22 of transistor O is connected to a second side 22' of capacitor C,. In addition, collector legs 20 and 22 are connected to a DC voltage source of V, volts at source point 29 through resistors R, and R respectively. In this preferred embodiment, the DC voltage source at point 29 is derived from an input signal, E,,,, by use of components included within the circuit as disclosed hereinbelow. It should be understood, however, that this invention also contemplates the use of independent conventional DC power supplies. Since the present invention is adapted to receive and respond to analog input signals, the input signal, if it has a sufficient DC component, may be suitable for deriving the circuits DC voltage source. This is typically the case when the input signal, E,,,, is an unregulated DC voltage which is to be regulated by the invented circuit. However, nothing precludes the use of a conventional DC power supply to provide power to the present invention independent of its input signal, E,,,.

The voltage V, at source point 29 is a substantially constant voltage, being equal'to the voltage across a zener diode 30 less the base-to-emitter voltage of a transistor Q V Transistor Q has an emitter leg 24, a collector leg 26 and a base leg 28. The collector leg 26 of transistor O is connected to an input point 23 to which the analog input signal, E,,,, is connected; the emitter leg 24 is connected through resistor R, to side 20' of capacitor C and the base leg 28 is connected to the positive side of zener diode 30, the latter maintaining a constant bias voltage on transistor 0,, causing it to be continuously in a fully conducting state. Zener diode 30 is energized by input signal voltage E, through a resistor R As indicated above, voltage V, could be provided by an independent DC power supply connected to point 29, thereby rendering components R,,, Q, and zener diode 30 unnecessary.

Transistors Q and Q, are utilized as current sources for the charging of capacitor C,. Transistors Q and Q, have emitter legs 32 and 34, collector legs 36 and 38, and base legs 40 and 42, respectively. The emitter leg 32 of transistor Q, is connected to the DC voltage source point 29 through resistor R the collector leg 36 to side 16' of capacitor C,; and the base leg 40 to a point 44, which is the junction point between divider resistors R and R serially connected between voltage source point 29 and circuit ground 15. Resistors R and R divide voltage V, by the ratio of to produce a voltage V at point 44. Voltage V is sufficient to bias transistor Q, into a continuously conducting state. The current i flowing through transistor 0,, first phase of each cycle, capacitor C is charged from to capacitor C, whenever transistor switch Q is in its the voltage source 29 through a first path defined by conducting state, is calculable as follows: charging resistor R and transistor switch 0,, the latter being in a fully conducting state. The charging rate is 5 determined by the time constant of the path, to wit:

(i) R C During this phase, the voltage on side of capacitor C is the relatively small colle'ctor-to-emitter voltage of transistor 0,, V (For all practical pur- (ii) poses, therefore, side 20 is at zero volts when the tranlO sistor switch O is conducting.) Thus, side 18 of capacwhere V is the base-to-emitter voltage of transistor itor C is the side where the charging takes place. At

i R the voltage across resistor R igRg V 3513) Q the start of the first phase of each cycle, the voltage on i 2 ua, side 18' is V,. The reason why the initial voltage on R3 side 18 is V, will become apparent when the electri- (iii) 5 cal dynamics at the end of the preceding cycle are described hereinbelow. The voltage on side 18' rises ex- Since V,, V ,V and R are substantially constant, ponentially from --V, toward +V,, the voltage level at i is a substantially constant current. the DC voltage source point 29. When the voltage on With reference to transistor 0,, emitter leg 34 is conside 18 of capacitor C reaches the base-to-ernitter nected through a resistor R to the input point 23; the 20 voltage of transistor switch Q ,VBE,, the latter is biased collector leg 38 to side 16' of capacitor C, and the base to its fully conducting state; whereas, prior to side 18 leg 42 to voltage source point 29. Voltage V, is suffireaching V volts, transistor switch Q is negatively cient to maintain transistor 0, continuously in a conbiased to a non-conducting state. While capacitor C is ducting state. The current i,, flowing through transistor charging, capacitor C, reaches a quiescent state where O to capacitor C, whenever transistor switch O is in 25 side 22 is at V, volts and side 16 is at the base-toits conducting state, is calculable as follows: emitter voltage of transistor (2,, V v

At the instant the voltage on the side 18' of capacitor R, the voltage across resistor R,

(iv) causing the voltage on side 22 of capacitor C, to instantly drop to the relatively small collector-emitter voltage of transistor Q in its conducting state. Since (v) the voltage on capacitor C, cannot change instantaneously, the voltage on side 16 must drop instantly to where V is the base-to-emitter voltage of transistor 3 V, volts. This negative voltage biases off transistor Q 5 switch Q,. Thus, at this instant, the first phase of the m i' BE4) cycle ends and the second phase begins. R4 The duration of the first phase of each cycle is calcu- (vi) lable from the following equation:

Thus, it can be seen that i, is directly proportional to 40 V1+ 2V1(1 the amplitude of the input signal E As will be ex- (vii) plained more fully hereinbelow, the current i +i where V is the voltage on side 18' of capacitor C charges capacitor C, during one of two portions of each as a function of time, 1.

cycle of operation of the invented circuit 10. Equation (vii) is the classical exponential charging Whereas capacitor C, is charged by current i +i function of an RC circuit with the appropriate initial whenever transistor switch Q is in a conducting state, condition included, to wit: at t 0, V,,, 'V,..

capacitor C is charged from the voltage source point The duration of the first phase, t,, equals the value of 29 through a charging resistor R whenever transistor t at which V equals V Thus,

switch Q, is in a conducting state. Resistor R, is connected between the voltage source point 29 and side V352: 1(

18 of capacitor C Resistors R and R are the usual (vim base resistors connected between base legs 16 and 18 4 IR c V V of transistors Q, and 0,, respectively, and the circuit 6 8 1 -'"2 ground 15. i I 1 (ix) A transistor 0,, Operating as an output switch has a collector leg 50, an emitter leg '52 and a base leg 54. By taking the logarithm of each side of equationtix); The collector leg 50 of transistor Q, is connected to l V,,,;,+ V, input 23; the base leg 54 to the collector leg 20 of tran- (tl/RBCZ) loge sistor switch 0,; and emitter leg 52 is the output termi- (X) nal of the invented circuit 10. The collector voltage V V Er of transistor switch Q, is used as a gating signal to t1: RBCZ loge 2V the base leg 54 of transistor Q Thus, the output 52 of 1 (ix) the invented circuit 10 is the input signal E,, as gated through transistor Q, by gating signal E Since R C V,,,;,, and V, are substantially constant,

C reaches V,,,;,, the transistor switch O is turned on,

. 6 The operation of embodiment 10 of the present mthe duration of the first phase of each cycle, t,, is a vention is now described. The operation is cyclic, each constant determined by selectable parameters of the cycle consisting of first and second phases. During the circuit 10.

During the second phase of each cycle, the side 16 of capacitor C, is charged from its initial value of V volts toward approximately +V volts by current i i flowing through transistor switch Q the latter being in a fully conducting state. During this phase, the voltage on side 22' of capacitor C is the relatively small collector-to-emitter of transistor Q1, V05 (For all practical purposes, therefore, side 22 is at zero volts when transistor switch Q is conducting.) The voltage on side 16 rises linearly as a function of charging current i i.,. When the voltage on side 16' reaches the base-toemitter voltage of transistor switch Q V 1 the latter is biased to its fully conducting state; whereas, prior to side 16 reaching V volts, transistor switch Q, is negatively biased to a non-conducting state. While capacitor C is charging, capacitor C reaches a quiescent state where side 20' is at V volts and side 18' is atV 9 volts. Thus, the operation of the circuit 10 during the second phase of each cycle, with respect to capacitor C and transistor switch Q is a mirror image of its operation during the first phase, with respect to capacitor C and transistor switch 0,, except that capacitor C, is charged by current 1}, i, which is directly proportional to the input signal voltage E i.e.,

i3 ii r' r VBE, IRQ) m/ 4) (14+ /R.)

' (xii) At the instant the voltage on the side 16 of capacitor C reaches V the transistor switch Q, is turned on, causing the voltage on side of capacitor C to instantly drop to the relatively small collector-to-emitter voltage of transistor Q, in its conducting state. Since the voltage on capacitor C cannot charge instantaneously, the voltage on side 18' must drop instantly to V volts; (hence, the reason why V, volts is the initial voltage on capacitor C at the start of the first phase of each cycle). This negative voltage biases off transistor switch Q At this instant, the second phase ends and the next cycle commences.

The duration of the second phase of each cycle is calculable from the following equation:

where lVw,

(xiv) The duration of the second phase, t equals the value of t at which v V Thus,

By making R t 5 (V R C /E ,,+V,V V (V R C /E V I (xviii) in 2 E R C V E Constant (xix) Thus, E t is approximately a constant value determined by selectable parameters of the circuit 10.

Gating signal E taken from the collector 20 of transistor 0,, has a waveform described as follows: For the,

fixed duration of I (referred to as the off-time), E is approximately zero volts, a level insufficient to turn on transistor gate Q Following the duration of the off time, E steps up to V volts and remains there for the duration of t (referred to as the on-time), V being sufficient to bias the transistor gate 0,, to a conducting state. Thus, for the duration of the on-time, the output E, at terminal 60 equals the input signal E,,,. It should be recognized that the off-time and ontime of the gating signal E and, therefore, of the output E, are the same as the first and second phases of each cycle described above. A load 62 is connected between the output terminal 60 and circuit ground 15.

The waveform of the output E, at terminal 60 is shown in FIG. 2. The off-time is designated 1,, and is a fixed interval. During t E is typically zero volts, except when load 62 provides no DC path to ground point 15. The on-time is designated t and is a variable func tion of the amplitude of E,,,( When E E t,,,, so as to yield an area under the voltage-time waveform equal to E X t,,,,,. Similarly, when E equals E and E during other cycles, the on-time of the respective cycles are t and to", where:

in X on ln X on in X om Constant Thus, it can be seen that the invented circuit 10 responds to the variable analog input signal E, by producing an output signal E having a substantially constant average amplitude, independent of variations in the amplitude of the input signal E One highly advantageous application of the present invention is as a switching regulator in, for example, computer power supplies wherein it provides essentially infinite line compensation. Such an application is schematically shown in FIG. 3. Preferred embodiment 10 is utilized in combination with a filter 68 comprising (i) a coupling transformer T, having primary and secondary windings 70 and 72, respectively; (ii) a power diode 74; and filter capacitor C where diode 74 and capacitor C, are serially connected to secondary 72.

The input to the primary winding 70 of transformer T is the output E of circuit whose waveform is shown in FIG. 2. Therefore, the energy into the filter 68 during each cycle is the product of E r and i where i is the current flowing through the primary winding 70 of transformer T. Thus;

Energy In E X X i,

(xxi) During the off-time of each cycle, substantially all of the energy stored in the primary winding 70 is transferred to the secondary 72 as the magnetic field collapses in the primary winding 70. Thus, the energy transferred to capacitor C, is approximately equal to the energy into the primary winding 70, disregarding small losses in transformer T and in diode 74. The energy into capacitor C, is the product of E t and i where E is the voltage induced across the secondary winding 72, and i is the current flowing through the secondary winding 72 to capacitor C,. Thus;

Energy into C,= E X i, X t E Energy In (xxii) Since Energy E,,, X t X i E x i X t E E r X i (xxiii) It is a well-known characteristic of transformers that the primary current and the secondary current are related to their respective turns by the following equation:

i Nf i2N2 (xxiv) where N and N are thenumber of turns of primary winding 70 and secondary winding 72 respectively. Thus;

2 h: X on oil) a 1) (xxv) The voltage across the capacitor C,, E is equal to E less the small voltage drop across the diode 74. Thus;

(xxvi) where k equals the constant turns ratio N /N Since it is the essential characteristic of circuit 10 to produce a constant E X 1, product during each cycle, and since r, is a constant determined by the selection of values of C and R in circuit 10, it is readily seen that E will remain constant, independent of variation of the input voltage E of course, this is precisely the function required of a switching regulator in computer or other power supplies.

Although this invention has been disclosed and described with reference to a particular embodiment, the principles involved are susceptible of other applications which will be apparent to persons skilled in the art. This invention, therefore, is not intended to be limited to the particular embodiment herein disclosed.

I claim: I

l. A variable duty-cycle and frequency oscillator circuit, adapted to receive an input signal at an input terminal and having an output terminal comprising:

a. a DC electrical power source derived from said input signal by means of a power transistor having base, emitter and collector legs, said collector leg thereof being electrically coupled to said input terminal, said base leg thereof being electrically connected to a zener diode which is electrically coupled to said input terminal, and said emitter leg thereof being connected to an output point of said DC power source, whereby said power transistor is continually biased to a conducting state by said zener diode and said voltage on said output point is substantially constant;

b. first and second transistors for switching, each of said transistors having base, collector and emitter legs, said collector legs of each being electrically coupled to said output point of said DC power source, said emitter legs of each being electrically connected to a circuit ground;

c. first and second capacitors, each having first and second sides, said first and second sides of said first capacitor being electrically coupled to said base leg of said first switching transistor and said collector leg of said second switching transistor, respectively, and said first and second sides of said second capacitor being electrically coupled to said base leg of said second switching transistor and said collector leg of said first switching transistor, respectively;

d. a source of current electrically coupled to said first side of said first capacitor, said current source comprising:

i. a third transistor having base, collector and emitter legs, said emitter leg thereof being electrically coupled to said input terminal, said base leg thereof being electrically coupled to said output point of said DC power source and said collector leg thereof being electrically coupled to said first side of said first capacitor;

ii. a pair of resistors serially disposed between said output point of said DC power source and said circuit ground, said resistors dividing the voltage of said DC power source; and

iii. a fourth transistor having base, collector and emitter legs, said emitter leg thereof being electrically coupled to said output point of said DC power source, said base leg thereof being electrically coupled to a'junction of said pair of resistors, and said collector leg thereof being electrically coupled to said first side of said first capaci tor, whereby said third and fourth transistors are continually in a conducting state, said third transistor providing a collector current which is directly proportional to the amplitude of said input signal, and said fourth transistor providing a substantially constant collector current.

e. a resistor electrically coupling said first side of said second capacitor to said DC power source; and

a fifth transistor for switching, said fifth transistor having base, collector and emitter legs, said collector leg thereof being electrically coupled to said input terminal, said emitter leg thereof being electrically coupled to said output terminal, and said base leg thereof being electrically coupled to said collector leg of said first transistor, whereby said first and second transistors each cyclically and alternately switching between conducting and nonconduc'ting states, said first transistor being in a conducting state and said second transistor being in a non-conducting state for a fixed time interval during each cycle of operation of said circuit, said fixed time interval being the time required for said first side of said second capacitor to be charged by said DC power source to a bias voltage which causes said second transistor to conduct, and said second transistor being in a conducting state and said first transistor being in a non-conducting state for a variable time interval during each cycle of said operation, said variable time interval being the time required for said first side of said first capacitor to be charged by said current source to a bias voltage which causes said first transistor to conduct, said variable time interval being inversely proportional to the amplitude of said. input signal, said cyclic switching of said first transistor causing said fifth transistor to be ina conducting state for said variable time interval and in a non-conducting state for said fixed interval, said inputsignal thereby appearing at said output terminal for said variable time interval of each cycle. I 

1. A variable duty-cycle and frequency oscillator circuit, adapted to receive an input signal at an input terminal and having an output terminal comprising: a. a DC electrical power source derived from said input signal by means of a power transistor having base, emitter and collector legs, said collector leg thereof being electrically coupled to said input terminal, said base leg thereof being electrically connected to a zener diode which is electrically coupled to said input terminal, and said emitter leg thereof being connected to an output point of said DC power source, whereby said power transistor is continually biased to a conducting state by said zener diode and said voltage on said output point is substantially constant; b. first and second transistors for switching, each of said transistors having base, collector and emitter legs, said collector legs of each being electrically coupled to said output point of said DC power source, said emitter legs of each being electrically connected to a circuit ground; c. first and second capacitors, each having first and second sides, said first and second sides of said first capacitor being electrically coupled to said base leg of said first switching transistor and said collector leg of said second switching transistor, respectively, and said first and second sides of said second capacitor being electrically coupled to said base leg of said second switching transistor and said collector leg of said first switching transistor, respectively; d. a source of current electrically coupled to said first side of said first capacitor, said current source comprising: i. a third transistor having base, collector and emitter legs, said emitter leg thereof being electrically coupled to said input terminal, said base leg thereof being electrically coupled to said output point of said DC power source and said collector leg thereof being electrically coupled to said first side of said first capacitor; ii. a pair of resistors serially disposed between said output point of said DC power source and said circuit ground, said resistors dividing the voltage of said DC power source; and iii. a fourth transistor having base, collector and emitter legs, said emitter leg thereof being electrically coupled to said output point of said DC power source, said base leg thereof being electrically coupled to a junction of said pair of resistors, and said collector leg thereof being electrically coupled to said first side of said first capacitor, whereby said third and fourth transistors are continually in a conducting state, said third transistor providing a collector current which is directly proportional to the amplitude of said input signal, and said fourth transistor providing a substantially constant collector current. e. a resistor electrically coupling said first side of said second capacitOr to said DC power source; and f. a fifth transistor for switching, said fifth transistor having base, collector and emitter legs, said collector leg thereof being electrically coupled to said input terminal, said emitter leg thereof being electrically coupled to said output terminal, and said base leg thereof being electrically coupled to said collector leg of said first transistor, whereby said first and second transistors each cyclically and alternately switching between conducting and non-conducting states, said first transistor being in a conducting state and said second transistor being in a non-conducting state for a fixed time interval during each cycle of operation of said circuit, said fixed time interval being the time required for said first side of said second capacitor to be charged by said DC power source to a bias voltage which causes said second transistor to conduct, and said second transistor being in a conducting state and said first transistor being in a non-conducting state for a variable time interval during each cycle of said operation, said variable time interval being the time required for said first side of said first capacitor to be charged by said current source to a bias voltage which causes said first transistor to conduct, said variable time interval being inversely proportional to the amplitude of said input signal, said cyclic switching of said first transistor causing said fifth transistor to be in a conducting state for said variable time interval and in a non-conducting state for said fixed interval, said input signal thereby appearing at said output terminal for said variable time interval of each cycle. 